`timescale 1ns / 1ps 
/**
 ******************************************************************************
 * @file    template_s_axi_lite.v
 * @author  KEN
 * @version V1.0
 * @date    Feb. 25th, 2020
 * @brief   Slave AXI-Lite Interface Template
 ******************************************************************************
 * @attention
 *
 * <h2><center>&copy; COPYRIGHT 2020 K'sP</center></h2>
 ******************************************************************************
 */

/*Template Start*/
/*

wire s_axi_lite_aclk;
wire s_axi_lite_aresetn;
wire [(C_ADDR_WIDTH - 1): 0] s_axi_lite_awaddr;
wire [2 : 0] s_axi_lite_awprot;
wire s_axi_lite_awvalid;
wire s_axi_lite_awready;
wire [(C_DATA_WIDTH - 1): 0] s_axi_lite_wdata;
wire [(C_DATA_WIDTH / 8 - 1): 0] s_axi_lite_wstrb;
wire s_axi_lite_wvalid;
wire s_axi_lite_wready;
wire [1 : 0] s_axi_lite_bresp;
wire s_axi_lite_bvalid;
wire s_axi_lite_bready;
wire [(C_ADDR_WIDTH - 1): 0] s_axi_lite_araddr;
wire [2 : 0] s_axi_lite_arprot;
wire s_axi_lite_arvalid;
wire s_axi_lite_arready;
wire [(C_DATA_WIDTH - 1): 0] s_axi_lite_rdata;
wire [1 : 0] s_axi_lite_rresp;
wire s_axi_lite_rvalid;
wire s_axi_lite_rready;

template_s_axi_lite
	#
	(
		.C_AXI_ADDR_WIDTH(C_ADDR_WIDTH),
		.C_AXI_DATA_WIDTH(C_DATA_WIDTH)
	)
	template_s_axi_lite_inst
	(
		.s_axi_lite_aclk(s_axi_lite_aclk),
		.s_axi_lite_aresetn(s_axi_lite_aresetn),
		//Write address channel. AWVALID, AWREADY, AWADDR, AWPROT
		.s_axi_lite_awvalid(s_axi_lite_awvalid),
		.s_axi_lite_awready(s_axi_lite_awready),
		.s_axi_lite_awaddr(s_axi_lite_awaddr),
		.s_axi_lite_awprot(s_axi_lite_awprot),
		//Write data channel. WVALID, WREADY, WDATA, WSTRB
		.s_axi_lite_wvalid(s_axi_lite_wvalid),
		.s_axi_lite_wready(s_axi_lite_wready),
		.s_axi_lite_wdata(s_axi_lite_wdata),
		.s_axi_lite_wstrb(s_axi_lite_wstrb),
		 //Write response channel. BVALID, BREADY, BRESP
		.s_axi_lite_bvalid(s_axi_lite_bvalid),
		.s_axi_lite_bready(s_axi_lite_bready),
		.s_axi_lite_bresp(s_axi_lite_bresp),
		//Read address channel. ARVALID, ARREADY, ARADDR, ARPROT
		.s_axi_lite_arvalid(s_axi_lite_arvalid),
		.s_axi_lite_arready(s_axi_lite_arready),
		.s_axi_lite_araddr(s_axi_lite_araddr),
		.s_axi_lite_arprot(s_axi_lite_arprot),
		//Read data channel. RVALID, RREADY, RDATA, RRESP
		.s_axi_lite_rvalid(s_axi_lite_rvalid),
		.s_axi_lite_rready(s_axi_lite_rready),
		.s_axi_lite_rdata(s_axi_lite_rdata),
		.s_axi_lite_rresp(s_axi_lite_rresp)
	);
	
*/
/*Template End*/

`define AXI_RESPOENSE_OKAY 2'b00
`define AXI_RESPOENSE_EXOKAY 2'b01
`define AXI_RESPOENSE_SLVERR 2'b10
`define AXI_RESPOENSE_DECERR 2'b11

module template_s_axi_lite
	   #(
		   /*Custom Parameters Defination*/
		   /*USER CODE BEGIN Parameters*/

		   /*USER CODE END Parameters*/

		   /*AXI Address Map Size, 2^(C_AXI_ADDR_WIDTH) Bytes*/
		   parameter integer C_AXI_ADDR_WIDTH = 5,
		   /*AXI Data Bus Size, C_AXI_DATA_WIDTH Bits*/
		   parameter integer C_AXI_DATA_WIDTH = 32
	   )
	   (
		   /*Custom Ports Defination*/
		   /*USER CODE BEGIN Ports*/
		   output wire ENABLE,
		   input wire BUSY,

		   output wire [31: 0] LENGTH,
		   output wire [31: 0] FREQ_WORD,
		   output wire [31: 0] TMS_MEM_ADDR,
		   output wire [31: 0] TDI_MEM_ADDR,
		   output wire [31: 0] TDO_MEM_ADDR,
		   
		   (* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 intr INTERRUPT" *)
		   (* X_INTERFACE_PARAMETER = "SENSITIVITY LEVEL_HIGH" *)
		   output wire intr,
		   /*USER CODE END Ports*/

		   //Global ACLK
		   (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s_axi_lite_aclk CLK" *)
		   (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF s_axi_lite, ASSOCIATED_RESET s_axi_lite_aresetn" *)
		   input wire s_axi_lite_aclk,
		   //Global ARESETn
		   (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s_axi_lite_aresetn RST" *)
		   (* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *)
		   input wire s_axi_lite_aresetn,

		   //Write address channel. AWVALID, AWREADY, AWADDR, AWPROT
		   (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_lite AWVALID" *)
		   input wire s_axi_lite_awvalid,
		   (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_lite AWREADY" *)
		   output wire s_axi_lite_awready,
		   (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_lite AWADDR" *)
		   input [(C_AXI_ADDR_WIDTH - 1): 0] s_axi_lite_awaddr,
		   (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_lite AWPROT" *)
		   input [2: 0] s_axi_lite_awprot,

		   //Write data channel. WVALID, WREADY, WDATA, WSTRB
		   (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_lite WVALID" *)
		   input wire s_axi_lite_wvalid,
		   (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_lite WREADY" *)
		   output wire s_axi_lite_wready,
		   (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_lite WDATA" *)
		   input wire [(C_AXI_DATA_WIDTH - 1): 0] s_axi_lite_wdata,
		   (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_lite WSTRB" *)
		   input wire [((C_AXI_DATA_WIDTH + 7) / 8 - 1): 0] s_axi_lite_wstrb,

		   //Write response channel. BVALID, BREADY, BRESP
		   (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_lite BVALID" *)
		   output wire s_axi_lite_bvalid,
		   (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_lite BREADY" *)
		   input wire s_axi_lite_bready,
		   (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_lite BRESP" *)
		   output wire [1: 0] s_axi_lite_bresp,

		   //Read address channel. ARVALID, ARREADY, ARADDR, ARPROT
		   (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_lite ARVALID" *)
		   input wire s_axi_lite_arvalid,
		   (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_lite ARREADY" *)
		   output wire s_axi_lite_arready,
		   (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_lite ARADDR" *)
		   input wire [(C_AXI_ADDR_WIDTH - 1): 0] s_axi_lite_araddr,
		   (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_lite ARPROT" *)
		   input wire [2: 0] s_axi_lite_arprot,

		   //Read data channel. RVALID, RREADY, RDATA, RRESP
		   (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_lite RVALID" *)
		   output wire s_axi_lite_rvalid,
		   (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_lite RREADY" *)
		   input wire s_axi_lite_rready,
		   (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_lite RDATA" *)
		   output wire [(C_AXI_DATA_WIDTH - 1): 0] s_axi_lite_rdata,
		   (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_lite RRESP" *)
		   output wire [1: 0] s_axi_lite_rresp
	   );

/*AXI Output Port Registers*/
reg awready_r;
reg wready_r;
reg bvalid_r;
reg [1: 0] bresp_r;

reg arready_r;
reg rvalid_r;
reg [(C_AXI_DATA_WIDTH - 1): 0] rdata_r;
reg [1: 0] rresp_r;

assign s_axi_lite_awready = awready_r;
assign s_axi_lite_wready = wready_r;
assign s_axi_lite_bvalid = bvalid_r;
assign s_axi_lite_bresp = bresp_r;

assign s_axi_lite_arready = arready_r;
assign s_axi_lite_rvalid = rvalid_r;
assign s_axi_lite_rdata = rdata_r;
assign s_axi_lite_rresp = rresp_r;

/*Write Process*/
reg [7: 0] aw_stage_r;
localparam integer AW_STAGE_WAIT_0 = 8'd0;
localparam integer AW_STAGE_RECVD = 8'd1;

reg aw_recvd_r;

reg [7: 0] w_stage_r;
localparam integer W_STAGE_WAIT_0 = 8'd0;
localparam integer W_STAGE_RECVD = 8'd1;

reg w_recvd_r;

//Write Enable Signal Generation
wire REG_WR_EN;
reg reg_wr_en_r; //User Register Write Enable

assign REG_WR_EN = reg_wr_en_r;

reg [7: 0] wresp_stage_r;
localparam integer WRESP_STAGE_WAIT_0 = 8'd0;
localparam integer WRESP_STAGE_SEND = 8'd1;
localparam integer WRESP_STAGE_END = 8'd2;

reg wresp_send_r;

reg [(C_AXI_ADDR_WIDTH - 1): 0] reg_waddr_now;

/*Write address channel*/
always@(posedge s_axi_lite_aclk or negedge s_axi_lite_aresetn)
begin
	if (~s_axi_lite_aresetn)
	begin
		awready_r <= 1'b1; //assert AWREADY before AWVALID

		aw_recvd_r <= 1'b0;
		aw_stage_r <= AW_STAGE_WAIT_0;
		
		reg_waddr_now <= 0;
	end
	else
	begin
		case (aw_stage_r)
			AW_STAGE_WAIT_0:
			begin
				if (s_axi_lite_awvalid)
				begin
					aw_stage_r <= AW_STAGE_RECVD;

					awready_r <= 1'b0;
					aw_recvd_r <= 1'b1;
					
					reg_waddr_now <= s_axi_lite_awaddr;
				end
			end

			AW_STAGE_RECVD:
			begin
				if (wresp_send_r)
				begin
					aw_stage_r <= AW_STAGE_WAIT_0;

					awready_r <= 1'b1;
					aw_recvd_r <= 1'b0;
				end
			end

		endcase
	end
end

/*Write data channel*/
always@(posedge s_axi_lite_aclk or negedge s_axi_lite_aresetn)
begin
	if (~s_axi_lite_aresetn)
	begin
		wready_r <= 1'b1; //assert WREADY befor WVALID

		w_recvd_r <= 1'b0;
		w_stage_r <= W_STAGE_WAIT_0;		
	end
	else
	begin
		case (w_stage_r)
			W_STAGE_WAIT_0:
			begin
				if (s_axi_lite_wvalid)
				begin
					w_stage_r <= W_STAGE_RECVD;

					wready_r <= 1'b0;
					w_recvd_r <= 1'b1;
				end
			end

			W_STAGE_RECVD:
			begin
				if (wresp_send_r)
				begin
					w_stage_r <= W_STAGE_WAIT_0;

					wready_r <= 1'b1;
					w_recvd_r <= 1'b0;
				end
			end

		endcase
	end
end

/*Write response channel*/
always@(posedge s_axi_lite_aclk or negedge s_axi_lite_aresetn)
begin
	if (~s_axi_lite_aresetn)
	begin
		bvalid_r <= 1'b0;
		bresp_r <= `AXI_RESPOENSE_OKAY;

		wresp_send_r <= 1'b0;
		wresp_stage_r <= WRESP_STAGE_WAIT_0;
		
		reg_wr_en_r <= 1'b0;
	end
	else
	begin
		case (wresp_stage_r)
			WRESP_STAGE_WAIT_0:
			begin
				//must wait for AWVALID, AWREADY, WVALID, WREADY to be asserted before assert BVALID
//				if (s_axi_lite_awvalid && s_axi_lite_awready && s_axi_lite_wvalid && s_axi_lite_wready)
//				if (((aw_recvd_r) || (s_axi_lite_awvalid && s_axi_lite_awready)) && (s_axi_lite_wvalid && s_axi_lite_wready))
				if((s_axi_lite_awvalid && s_axi_lite_awready && s_axi_lite_wvalid && s_axi_lite_wready) ||
					(aw_recvd_r && s_axi_lite_wvalid && s_axi_lite_wready) ||
					(s_axi_lite_awvalid && s_axi_lite_awready && w_recvd_r))
				begin
					wresp_stage_r <= WRESP_STAGE_SEND;

					bvalid_r <= 1'b1;

					bresp_r <= `AXI_RESPOENSE_OKAY;
					
					reg_wr_en_r <= 1'b1;
				end
			end

			WRESP_STAGE_SEND:
			begin
				reg_wr_en_r <= 1'b0;
				
				if (s_axi_lite_bready)
				begin
					wresp_stage_r <= WRESP_STAGE_END;
					wresp_send_r <= 1'b1;

					bvalid_r <= 1'b0;
				end
			end

			WRESP_STAGE_END:
			begin
				if (~aw_recvd_r && ~w_recvd_r)
				begin
					wresp_send_r <= 1'b0;
					wresp_stage_r <= WRESP_STAGE_WAIT_0;
				end
			end

		endcase
	end
end

/*Read Process*/
reg [7: 0] ar_stage_r;
localparam integer AR_STAGE_WAIT_0 = 8'd0;
localparam integer AR_STAGE_RECVD = 8'd1;

reg ar_recvd_r;

reg [7: 0] r_stage_r;
localparam integer R_STAGE_WAIT_0 = 8'd0;
localparam integer R_STAGE_SEND = 8'd1;
localparam integer R_STAGE_END = 8'd2;

reg r_send_r;

reg [(C_AXI_ADDR_WIDTH - 1): 0] reg_raddr_now;

/*Read address channel*/
always@(posedge s_axi_lite_aclk or negedge s_axi_lite_aresetn)
begin
	if (~s_axi_lite_aresetn)
	begin
		arready_r <= 1'b1;

		ar_recvd_r <= 1'b0;
		ar_stage_r <= AR_STAGE_WAIT_0;
		
		reg_raddr_now <= 0;
	end
	else
	begin
		case (ar_stage_r)
			AR_STAGE_WAIT_0:
			begin
				if (s_axi_lite_arvalid == 1'b1)
				begin
					ar_stage_r <= AR_STAGE_RECVD;

					arready_r <= 1'b0;
					ar_recvd_r <= 1'b1;
					
					reg_raddr_now <= s_axi_lite_araddr;
				end
			end

			AR_STAGE_RECVD:
			begin
				if (r_send_r)
				begin
					ar_stage_r <= AR_STAGE_WAIT_0;

					arready_r <= 1'b1;
					ar_recvd_r <= 1'b0;
				end
			end

		endcase
	end
end

/*Read data channel*/
always@(posedge s_axi_lite_aclk or negedge s_axi_lite_aresetn)
begin
	if (~s_axi_lite_aresetn)
	begin
		rvalid_r <= 1'b0;

		r_send_r <= 1'b0;
		r_stage_r <= R_STAGE_WAIT_0;
	end
	else
	begin
		case (r_stage_r)
			R_STAGE_WAIT_0:
			begin
				//must wait for ARVALID and ARREADY before assert RVALID
				if (s_axi_lite_arvalid && s_axi_lite_arready)
				begin
					r_stage_r <= R_STAGE_SEND;

					rvalid_r <= 1'b1;
					r_send_r <= 1'b1;
				end
			end

			R_STAGE_SEND:
			begin
				if (s_axi_lite_rready)
				begin
					r_stage_r <= R_STAGE_END;

					rvalid_r <= 1'b0;
				end
			end

			R_STAGE_END:
			begin
				if (~ar_recvd_r)
				begin
					r_send_r <= 1'b0;
					r_stage_r <= R_STAGE_WAIT_0;
				end
			end

		endcase
	end
end

/***************************************************************/
//User Register Map Handler
/***************************************************************/
/*USER CODE BEGIN 0*/
reg [(C_AXI_DATA_WIDTH - 1): 0] reg_cr_r;
reg [(C_AXI_DATA_WIDTH - 1): 0] reg_length_r;
reg [(C_AXI_DATA_WIDTH - 1): 0] reg_freq_word_r;
reg [(C_AXI_DATA_WIDTH - 1): 0] reg_tms_mem_addr_r;
reg [(C_AXI_DATA_WIDTH - 1): 0] reg_tdi_mem_addr_r;
reg [(C_AXI_DATA_WIDTH - 1): 0] reg_tdo_mem_addr_r;

localparam integer REG_CR_ENABLE = 0;
localparam integer REG_CR_INT_EN = 1;
localparam integer REG_CR_INT_STATUS = 2;

reg [1:0] en_self_clr_state;

/*USER CODE END 0*/

integer wr_byte_index;

//Write Register Map
always@(posedge s_axi_lite_aclk or negedge s_axi_lite_aresetn)
begin
	if (~s_axi_lite_aresetn)
	begin
		reg_cr_r <= 0;
		reg_length_r <= 0;
		reg_freq_word_r <= 0;
		reg_tms_mem_addr_r <= 0;
		reg_tdi_mem_addr_r <= 0;
		reg_tdo_mem_addr_r <= 0;
		
		en_self_clr_state <= 0;
	end
	else
	begin
		if (REG_WR_EN)
		begin
			en_self_clr_state <= 0;
			
			//Register Address 4/8 Bytes Aligned
			case (reg_waddr_now[(C_AXI_ADDR_WIDTH - 1): (C_AXI_DATA_WIDTH / 32 + 1)])
				/*USER CODE BEGIN 1*/
				0:
				begin
					for ( wr_byte_index = 0; wr_byte_index < (C_AXI_DATA_WIDTH + 7) / 8; wr_byte_index = wr_byte_index + 1 )
					begin
						if ( s_axi_lite_wstrb[wr_byte_index] == 1 )
						begin
							// Slave register 0
							reg_cr_r[(wr_byte_index * 8) +: 8] <= s_axi_lite_wdata[(wr_byte_index * 8) +: 8];
						end
					end
				end

				1:
				begin
					for ( wr_byte_index = 0; wr_byte_index < (C_AXI_DATA_WIDTH + 7) / 8; wr_byte_index = wr_byte_index + 1 )
					begin
						if ( s_axi_lite_wstrb[wr_byte_index] == 1 )
						begin
							// Slave register 1
							reg_length_r[(wr_byte_index * 8) +: 8] <= s_axi_lite_wdata[(wr_byte_index * 8) +: 8];
						end
					end
				end

				2:
				begin
					for ( wr_byte_index = 0; wr_byte_index < (C_AXI_DATA_WIDTH + 7) / 8; wr_byte_index = wr_byte_index + 1 )
					begin
						if ( s_axi_lite_wstrb[wr_byte_index] == 1 )
						begin
							// Slave register 2
							reg_freq_word_r[(wr_byte_index * 8) +: 8] <= s_axi_lite_wdata[(wr_byte_index * 8) +: 8];
						end
					end
				end

				3:
				begin
					for ( wr_byte_index = 0; wr_byte_index < (C_AXI_DATA_WIDTH + 7) / 8; wr_byte_index = wr_byte_index + 1 )
					begin
						if ( s_axi_lite_wstrb[wr_byte_index] == 1 )
						begin
							// Slave register 3
							reg_tms_mem_addr_r[(wr_byte_index * 8) +: 8] <= s_axi_lite_wdata[(wr_byte_index * 8) +: 8];
						end
					end
				end
				
				4:
				begin
					for ( wr_byte_index = 0; wr_byte_index < (C_AXI_DATA_WIDTH + 7) / 8; wr_byte_index = wr_byte_index + 1 )
					begin
						if ( s_axi_lite_wstrb[wr_byte_index] == 1 )
						begin
							// Slave register 4
							reg_tdi_mem_addr_r[(wr_byte_index * 8) +: 8] <= s_axi_lite_wdata[(wr_byte_index * 8) +: 8];
						end
					end
				end
				
				5:
				begin
					for ( wr_byte_index = 0; wr_byte_index < (C_AXI_DATA_WIDTH + 7) / 8; wr_byte_index = wr_byte_index + 1 )
					begin
						if ( s_axi_lite_wstrb[wr_byte_index] == 1 )
						begin
							// Slave register 5
							reg_tdo_mem_addr_r[(wr_byte_index * 8) +: 8] <= s_axi_lite_wdata[(wr_byte_index * 8) +: 8];
						end
					end
				end
				
				/*USER CODE END 1*/

				default:
				begin
					/*USER CODE BEGIN 2*/

					/*USER CODE END 2*/
				end

			endcase
		end
		else
		begin
			case(en_self_clr_state)
				0:
				begin
					if(ENABLE)
					begin
						reg_cr_r[REG_CR_INT_STATUS] <= 1'b0;
						
						en_self_clr_state <= 1;
					end
				end
				
				1:
				begin
					if(BUSY)
					begin
						en_self_clr_state <= 2;
					end
				end
				
				2:
				begin
					if(~BUSY)
					begin
						reg_cr_r[REG_CR_ENABLE] <= 1'b0;
						reg_cr_r[REG_CR_INT_STATUS] <= 1'b1;
						
						en_self_clr_state <= 0;
					end
				end
				
				default:
				begin
					en_self_clr_state <= 0;
				end
			endcase
		end
	end
end

/*Read Register Map*/
always@( * )
begin
	case (reg_raddr_now[(C_AXI_ADDR_WIDTH - 1): (C_AXI_DATA_WIDTH / 32 + 1)])
		/*USER CODE BEGIN 3*/
		0:
		begin
			rdata_r <= reg_cr_r;
			rresp_r <= `AXI_RESPOENSE_OKAY;
		end

		1:
		begin
			rdata_r <= reg_length_r;
			rresp_r <= `AXI_RESPOENSE_OKAY;
		end

		2:
		begin
			rdata_r <= reg_freq_word_r;
			rresp_r <= `AXI_RESPOENSE_OKAY;
		end

		3:
		begin
			rdata_r <= reg_tms_mem_addr_r;
			rresp_r <= `AXI_RESPOENSE_OKAY;
		end

		4:
		begin
			rdata_r <= reg_tdi_mem_addr_r;
			rresp_r <= `AXI_RESPOENSE_OKAY;
		end
		
		5:
		begin
			rdata_r <= reg_tdo_mem_addr_r;
			rresp_r <= `AXI_RESPOENSE_OKAY;
		end

		/*USER CODE END 3*/

		default:
		begin
			//unmapped address
			rdata_r <= 0;
			rresp_r <= `AXI_RESPOENSE_SLVERR;
		end

	endcase
end


assign ENABLE = reg_cr_r[REG_CR_ENABLE];
assign LENGTH = reg_length_r;
assign FREQ_WORD = reg_freq_word_r;
assign TMS_MEM_ADDR = reg_tms_mem_addr_r;
assign TDI_MEM_ADDR = reg_tdi_mem_addr_r;
assign TDO_MEM_ADDR = reg_tdo_mem_addr_r;

assign intr = reg_cr_r[REG_CR_INT_EN] ? reg_cr_r[REG_CR_INT_STATUS] : 1'b0;

endmodule